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X28HC256
LAST
WE
CE
OE
WRITE
I/O 6
*
V OH
V OL
HIGH Z
*
X28C512, X28C513
READY
* I/O 6 Beginning and ending state of I/O 6 will vary.
FIGURE 4. TOGGLE BIT BUS SEQUENCE
?
LAST WRITE
YES
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
The internal software data protection circuit is enabled after
the first write operation, utilizing the software algorithm. This
circuit is nonvolatile, and will remain set for the life of the
device unless the reset command is issued.
Once the software protection is enabled, the X28HC256 is
also protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be
issued prior to writing additional data to the device.
Software Algorithm
Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figures 6 and 7 for the sequence. The three-byte sequence
opens the page write window, enabling the host to write from
COMPARE
OK?
YES
NO
one to one hundred twenty-eight bytes of data. Once the
page load cycle has been completed, the device will
automatically be returned to the data protected state.
X28C256
READY
FIGURE 5. TOGGLE BIT SOFTWARE FLOW
Software Data Protection
The X28HC256 offers a software-controlled data protection
feature. The X28HC256 is shipped from Intersil with the
software data protection NOT ENABLED; that is, the device
will be in the standard operating mode. In this mode data
should be protected during power-up/down operations
through the use of external circuits. The host would then
have open read and write access of the device once V CC
was stable.
The X28HC256 can be automatically protected during
power-up and power-down (without the need for external
circuits) by employing the software data protection feature.
6
FN8108.3
September 21, 2011
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